Documentación avanzada

Técnicas básicas de codificación en HDL (VHDL , VERILOG)
Técnicas básicas de codificación en HDL para SPARTAN 3e (VHDL , VERILOG)
Vídeos de entrenamiento gratuitos (FPGA, DSP and Embedded design)
User Guide UG612 (v 14.3) October 16, 2012 (Timing Closure User Guide)

User Guide UG230 (v1.2) January 20, 2011 Spartan-3E FPGA Starter Kit Board User Guide
User Guide UG627 (v 14.5) March 20, 2013  XST User Guide for Virtex-4,Virtex-5, Spartan-3, and newer CPLD Devices
User Guide UG331 (v1.8) June 13, 2011 Spartan-3 Generation FPGA User Guide
User Guide UG332 (v1.6) October 26, 2009 Spartan-3 Generation Configuration User Guide
User Guide UG625 (v. 14.5) April 1, 2013 Contraints Guide  ISE Design Suite 14.5 through 14.7
Documentación y respuestas Spartan 3e
Cool Runner II (Spartan 3e Saterter Kit) CPLD Practicas de laboratorio (Bogotá)
A Look Inside: SoC FPGAs Introduction (Part 1 of 5)
ECE5760 FPGA lectures 2011
FPGA/Verilog student projects Cornell University 2014
Canal of Bruce Land from Cornell University
Masters of Engineering Projects (Bruce Lander)
RAM on DE2 Cyclone (Bruce Lander)